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XC3000L Low Voltage Logic Cell Array Family
Product Specifications
Features
Description
The XC3000L family of FPGAs is optimized for operation from a nominally 3.3 V supply. Aside from the electrical and timing parameters listed in this data sheet, the XC3000L family is in all respects identical with the XC3000A family, and is a superset of the XC3000 family. The operating power consumption of Xilinx FPGAs is almost exclusively dynamic, and it changes with the square of the supply voltage. For a given complexity and clock speed, the XC3000L consumes, therefore, only 44% of the power used by the equivalent XC3000A device. In accordance with its use in battery-powered equipment, the XC3000L family was designed for the lowest possible power-down and quiescent current consumption. In mixed supply-voltage systems, the XC3000L, fed by a 3.3 V (nominal) supply, can directly drive any device with TTL-like input thresholds. When a 5 V device drives the XC3000L, a current-limiting resistor (1 k) or a voltage divider is required to prevent excessive input current. Like the XC3000A family, XC3000L offers the following functional improvements over the popular XC3000 family: The XC3000L family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3000L devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option. The XC3000L family is a superset of the XC3000 family. Any bitstream used to configure an XC3000 device configures an XC3000L device the same way.
* Part of the ZERO+ family of 3.3 V FPGAs * Low supply voltage FPGA family with five device
types - JEDEC-compliant 3.3 V version of theXC3000A LCA Family - Logic densities from 1,000 to 6,000 gates - Up to 144 user-definable I/Os
* Advanced, low power 0.8 CMOS static memory
technology - Very low quiescent current consumption, 20A - Operating power consumption 56% less than XC3000A, 66% less than previous generation 5 V FPGAs
* Superset of the industry-leading XC3000 family
- Identical to the basic XC3000 in structure, pinout, design methodology, and software tools - 100% compatible with all XC3000, XC3000A, XC3100 and XC3100A bitstreams - Improved routing and additional features
* Additional programmable interconnection points
(PIPs) - Improved access to Longlines and CLB clock enable inputs - Most efficient XC3000-class solution to bus-oriented designs
* XC3000L-specific features
Guaranteed over the 3.0 to 3.6 V Vcc range 4 mA output sink and source current Error checking of the configuration bitstream Soft startup starts all outputs in slew-limited mode upon power-up - Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production - - - -
Device XC3020L XC3030L XC3042L XC3064L XC3090L
CLBs 64 100 144 224 320
Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20
User I/Os Max 64 80 96 120 144
Flip-Flops 256 360 480 688 928
Horizontal Longlines 16 20 24 32 40
Configurable Data Bits 14,779 22,176 30,784 46,064 64,160
2-169
XC3000L Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description VCC VIN VTS TSTG TSOL Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic TJ Junction temperature ceramic +150 -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 Units V V V C C C C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage Low-level input voltage Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC +0.3 0.8 250 Units V V V ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. Although the present (1994) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclude operation at 5 V.
2-170
DC Characteristics Over Operating Conditions
Symbol VOH VOL VOH VOL VCCPD ICCPD ICCO IIL CIN
Description High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ -100 A, VCC min) Low-level output voltage (@ 100 A, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Quiescent LCA supply current* Chip thresholds programmed as CMOS levels Input Leakage Current, all I/O pins in parallel Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2
Min 2.40
Max
Units V
0.40 VCC -0.2 0.2 2.30 10
V V V V A
20 -10 +10
A A
10 15
pF pF
15 20 0.02 0.17 2.50
pF pF mA mA
IRIN IRLL
Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low
* With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA device configured with a MakeBits tie option. ICCO is in addition to ICCPD.
2-171
XC3000L Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO
CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)
X5424
T
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade Description Global and Alternate Clock Distribution* Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)* I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Symbol -8 Max Units
TPGC TPGCC
9.0 7 .0
ns ns
TIO TON TPUS
5 .0 12 .0 24 .0
ns ns ns
TBIDI
2 .0
ns
* Timing is based on the XC3042L, for other devices see XACT timing calculator. Note: The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid design option for XC3000L devices
2-172
.
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG MODE F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables Data In Enable Clock Symbol Min
-8 Max Units
1
TILO
6.7 7.5
ns ns
8
TCKO
7.5
ns
TQLO
14.0 14.8
ns ns
2 4 6
TICK TDICK TECCK
5.0 5.8 5.0 5.0
ns ns ns ns
A, B, C, D, E DI EC
3 5 7
TCKI TCKDI TCKEC
0 2.0 2.0
ns ns ns
Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)* RESET width (Low) delay from RESET pad to outputs X or Y
11 12
TCH TCL FCLK
5.0 5.0 80.0
ns ns MHz
13 9
TRPW TRIO
7.0 7.0
ns ns
TMRW TMRQ
16.0 23.0
ns ns
*Timing is based on the XC3042A, for other devices see XACT timing calculator. Notes: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2-173
XC3000L Logic Cell Array Family
IOB Switching Characteristic Guidelines
I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID
I/O Pad TS 8 I/O Pad Output
X5425
TTSON
9
T TSHZ
Vcc PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
2-174
IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042L) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) Symbol Min
-8 Max Min Max Min Max Units
3 4
TPID TPTG TIKRI
5.0 24.0 6.0
ns ns ns
1
TPICK
22.0
ns
7 7 10 10 9 9 8 8
TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON
12.0 28.0 9.0 25.0 12.0 28.0 16.0 32.0
ns ns ns ns ns ns ns ns
5 6
TOOK TOKO
12.0 0
ns ns
11 12
TIOH TIOL FCLK
5.0 5.0 80.0
ns ns MHz
13 15 15
TRRI TRPO TRPO
25.0 35.0 51.0
ns ns ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized. 4. The slew-limited delays for TOKPO, TSHZ, TTSON, and TRPO are guaranteed by design and not tested.
2-175
XC3000L Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. For package physical dimensions and thermal data, see Section 4.
Ordering Information
Example: Device Type Block Delay
XC3042L-8VQ100C
Temperature Range
Number of Pins
Package Type
Component Availability
PINS TYPE
44
PLAST. PLCC
64
PLAST. VQFP
68
PLAST. PLCC
84
PLAST. PLCC CERAM PLAST. PGA PQFP
100
PLAST. TQFP
132
144
160
164
175
176
208
223
TOPPLAST. BRAZED PLAST. CERAM. PLAST. VQFP CQFP PGA PGA TQFP
TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP PGA PGA TQFP
PLAST. CERAM. PQFP PGA
CODE
PC44
VQ64
C
PC68
PC84
C C C C C
PG84
PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
C C C C C
XC3020L XC3030L XC3042L XC3064L XC3090L
C = Commercial = 0 to +70 C
I = Industrial = -40 to +85 C
M = Mil Temp = -55 to +125 C
B = MIL-STD-883C Class B
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